1. Field of the Invention
Embodiments of the present invention relate to a method for manufacturing integrated circuit devices. More particularly, embodiments of the invention relate to forming metal interconnect structures having a barrier layer contacting at least a part of a dielectric layer.
2. Description of the Related Art
As the structure size of integrated circuit (IC) devices is scaled down to sub-quarter micron dimensions, electrical resistance and current densities have become an area for concern and improvement. Multilevel interconnect technology is used to form high aspect ratio features, including contacts, plugs, vias, lines, wires, and other features. A typical process for forming an interconnect on a substrate includes depositing one or more layers, etching at least one of the layer(s) to form one or more features, depositing a barrier layer in the feature(s) and depositing one or more layers to fill the feature. Typically, a feature is formed within a dielectric material disposed between a lower conductive layer and an upper conductive layer. The interconnect is formed within the feature to link the upper and lower conductive layers. Reliable formation of these interconnect features is important to the production of the circuits and is instrumental in the continued effort to increase circuit density and quality.
Copper has recently become a choice metal for filling sub-micron, high aspect ratio interconnect features because copper and its alloys have lower resistivities than aluminum. However, copper diffuses more readily into surrounding materials and can alter the electronic device characteristics of the adjacent layers. For example, such diffusion can form a conductive path between layers, thereby reducing the reliability of the overall circuit and possibly cause device failure.
Barrier layers are deposited prior to copper metallization to prevent or impede the diffusion of copper atoms. Barrier layers typically contain a refractory metal such as tungsten, titanium, tantalum, and nitrides thereof, which all have a greater resistivity than copper. To deposit a barrier layer within a feature, the barrier layer must be deposited on the bottom and sidewalls of the feature. The addition of the barrier layer on the bottom of the feature not only increases the overall resistance of the feature, but also forms an obstruction between higher and lower metal interconnects of a multi-layered interconnect structure.
The barrier layers are often deposited on dielectric layers that have been etched to include one or more features. The dielectric layers are typically formed of low k (dielectric constant k≦4.0) material. The low k layers may be porous layers. During the deposition of a barrier layer over a porous low k layer, the precursors used to form the barrier layer can diffuse into the pores of the porous low k layer. As with the diffusion of copper discussed earlier, the diffusion of barrier materials is problematic. The diffusion of barrier layer precursors into the porous low k layer can raise the dielectric constant of the low k layer, resulting in, for example, current leakage in a device.
The deposition of barrier layers can also be a time-consuming step, as the initial deposition or nucleation of barrier layers can be slow.
There is a need, therefore, for a processing sequence in which a barrier layer is deposited on a dielectric layer such that the diffusion of barrier layer precursors into the dielectric layer is minimized. There is also a need for a process sequence in which a barrier layer is deposited on a dielectric layer at a faster rate.